The present invention relates to a multilayer printed wiring board, particularly one used for semiconductor chip package, and a process for producing such a wiring board.
Multilayer printed wiring board usually comprises an insulating substrate, a power layer, a ground layer, circuit conductors formed on the surface thereof, inner layer circuits, via holes or through-holes for making electrical connection of the circuits in the respective layers, and solder resists for insulating the surface circuits.
Various methods are available for the manufacture of multilayer printed wiring boards such as mentioned above. For example, a method is popularly known which comprises forming the inner circuits and interlayer circuit boards including a power layer and a ground layer by etching away unnecessary parts of the copper foil of a copper-clad laminate, placing thereon a prepreg and a copper foil in layers, integrally laminating them by heating under pressure, forming openings at the parts where electrical connection is to be made, metallizing the inner walls of said openings by electroless plating or other means, etching away the unnecessary parts of the copper foil on the surface, then coating a solder resist thereon and drying the same.
In another commonly practiced method, the inner layer circuits of the respective layers are formed separately and positioned by using guide pins, and after integral lamination, the through-holes, outer layer circuits and solder resist are formed.
Regarding semiconductor chip packages, Japanese Patent Application Kokai (Laid-Open) [JP-A-] No. 59-158579 discloses a leadless chip carrier in which the terminals connected to semiconductor chips are extended out from the inside to a part on the outside of the package.
Japanese Patent Application Kokoku (Publication) [JP-B-]No. 58-11100 discloses a pin grid array having a plurality of terminal pins for connection to the through-holes in other package-carrying wiring boards, and a process for producing such an array. This patent also presents a ball grid array in which solder balls are fused to the lands instead of pins in the pin grid array to make electrical connection by soldering.
JP-B-58-26828 discloses a tape automatic carrier constituted by first forming the terminal strips and then insulating them with a tape-like insulating film.
In most of these semiconductor chip packages (hereinafter referred to as "chip carriers"), a ceramic material has been used for insulators and electrical connection of these chip carriers to semiconductor chip terminals has been made by wire bonding. Organic insulating material has been used as sealant for protecting the semiconductor chips and electrical connections from the environment after the semiconductor chips have been mounted on said chip carriers.
Recently, in view of economical disadvantages of ceramic chip carriers due to the increased number of steps for calcination, there have been developed chip carrier producing methods incorporating the ordinary multilayer wiring board manufacturing techniques using an organic insulating material. For instance, a method for producing pin grid array packages is disclosed in JP-B-3-25023.
Necessity has become acute recently for increased density of wiring and size reduction of wiring boards to meet the request for smaller size and functional multiplication of electronic devices. Smaller thickness is also required of the insulators used for interlayer insulation between the inner layer circuits. The conventional prepregs using woven or non-woven glass fabrics are capable of answering to such request for size reduction, and it is therefore attempted to apply an insulating resin or to use a film of insulating resin.
However, when an insulator not containing a reinforcement such as woven or non-woven glass fabrics is used for interlayer insulation, the produced laminate becomes more likely to suffer exfoliation or generation of voids due to heat history of the adjoining insulating layers.
This phenomenon tends to occur particularly when the through-holes are formed in the multilayer wiring board or when many via holes are formed in the layers containing no reinforcement such as woven or non-woven glass fabrics.